Forming electrodes to small electronic devices having self-assembled organic layers

ABSTRACT

In one embodiment of the invention, a method of fabricating a SAM device comprises the steps of: (a) providing a substrate having a top surface and a first metal electrode disposed on the top surface, (b) annealing the first metal electrode, (c) forming a SAM layer on a major surface of the first electrode, the SAM layer having a free surface such that the SAM is disposed between the free surface and the major surface of the first electrode, and (d) forming a second metal electrode on the free surface of the molecular layer. Forming step (d) includes the step of (d 1 ) depositing the second metal electrode in at least two distinct depositions separated by an interruption period of time when essentially no deposition of the second metal takes place. SAM FETs fabricated using this method are also described.

BACKGROUND OF THE INVENTION Field of the Invention

This invention relates to forming electrodes to electronic devices and,more particularly, to forming electrodes to small electronic devicesthat include thin self-assembled organic layers.

REFERENCES

In the following sections cross-reference is made to each of thefollowing references, each of which is incorporated herein in itsentirety. Each cross-reference is made by bracketing the number(s) inthe following list corresponding to the cited reference(s).

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DISCUSSION OF THE RELATED ART

Reliable and scalable integration of organic molecules within nanoscaleelectronic devices has the potential to dramatically expand availabledevice functionality. Similar to other device platforms, such asSi-based technology, the electronic properties of devices that are justa few atomic layers thick are determined not solely by the host materialbut also by dopants, defects and electronic states at interfaces.Incorporation of molecules in small devices calls for the simultaneoussolution of many interrelated material, electronic and chemical issues.

One type of nanoscale device (e.g., an FET) is built of self-assembledmolecular (SAM) layers disposed between two metal electrodes [1-3].Typically, organic molecules do not have electronic states at energiesclose to the Fermi energy level of common metals. Instead ofconventional band-to-band conduction, electrons travel between the metalelectrodes by tunneling through the molecules in the gap between thehighest occupied molecular orbital (HOMO) and the lowest unoccupiedmolecular orbital (LUMO). Tunneling transmission is governed by theenergy difference between the Fermi level of the contacts and theclosest molecular orbital and by the spatial extent of the molecularorbital. Because tunneling transmission is exponentially related toenergy and distance, the conductance of real devices can be much largeror much smaller than that produced by molecular tunneling.

A single defect state in a molecular layer with defect energy close tothe Fermi level can dramatically increase the transmission. The mostcommon origin of defects in molecular devices is penetration of metalfrom the contacts into the molecular layer. The penetrating metaltypically has one of three forms: (1) a filament, by which I mean ananoscale metal wire that connects the source and drain electrodes toone another, thereby fully shorting the device; (2) a particle, by whichI mean a nanoscale metal piece within a SAM layer but not connected toeither the source or drain electrode; or (3) a protrusion, by which Imean a nanoscale metal piece connected to either the source or drainelectrode, but not both. A protrusion may be merely a microscopicdeviation of an electrode surface from perfect flatness, or it may be acluster of metal atoms attached to the electrode surface.

For example, during and after fabrication, filaments can form, eithercompletely shorting the source and the drain electrodes and limiting theyield of useful FET devices [4, 5] or strongly increasing deviceconductance [6], or particles can penetrate into the SAM layers [7]. Inthe process of metal contact growth and crystallization the electrodemay protrude into the SAM layer, thus deforming molecules and affectingconductance [8]. Distorted chemical bonds at the interface between metaland molecule can decrease the tunneling transmission.

In addition, metal films commonly used as electrodes (e.g., Au, Ag, Ti,and Pt) grow and interact very differently on top of SAM layers [9-12].Currently, every experiment is unique in that the placement of theatoms/molecules of the relevant device constituents (e.g., metalcontacts, SAM layers, and uncontrolled impurities) cannot be determinedaccurately.

Thus, a need remains in the art for a technique that allows electrodesto be formed on SAM devices without the adverse effects discussed above;that is, without shorting the devices or increasing tunnelingconductance significantly.

BRIEF SUMMARY OF THE INVENTION

In accordance with one aspect of my invention, I have discovered afabrication process that addresses the prior art difficulties in makingreliable electrical contact to a SAM layer. In one embodiment, a methodof fabricating a SAM device comprises the steps of: (a) providing asubstrate having a top surface and a first metal electrode disposed onthe top surface, (b) annealing the first metal electrode, (c) forming aSAM layer on a major surface of the first electrode, the SAM layerhaving a free surface such that the self-aligned molecules are disposedbetween the free surface and the major surface of the first electrode,and (d) forming a second metal electrode on the free surface of themolecular layer. Forming-step-(d) includes the step of (d1) depositingthe second metal electrode in at least two distinct depositionsseparated by an interruption period of time when essentially nodeposition of the second metal takes place.

In accordance with another aspect of my invention, apparatus comprises asubstrate having a top surface and first metal electrode disposed on atleast a portion of the top surface, the first metal electrode having anannealed crystal structure. A SAM layer is disposed on a major surfaceof the first metal electrode, the SAM layer having a free surface suchthat the self-aligned molecules are interposed between the free surfaceand the major surface. A second metal electrode has at least a portionthereof disposed on the free surface of the SAM layer. Importantly, theportion of the second metal electrode includes metal clusters.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

My invention, together with its various features and advantages, can bereadily understood from the following more detailed description taken inconjunction with the accompanying drawing, in which:

FIG. 1 illustrates a prior art process sequence for forming a SAM layeron a metal layer, as shown in FIG. 1 d;

FIG. 2 is a schematic, side view of a prior art SAM device;

FIG. 3 is a schematic, cross-sectional view of a SAM FET, in accordancewith one embodiment of my invention;

FIG. 4 illustrates the fabrication of templates and molecular junctions,in accordance with another embodiment of my invention; FIGS. 4 a-4 cshow schematically a stencil mask (template) defined within a stack ofinsulating layers formed on a Si substrate; FIGS. 4 b and 4 c arepartially cut away; FIGS. 4 d-4 f show the fabrication of a SAM junctionusing the template of FIG. 4 c; FIG. 4 d zooms in on the central regionof FIG. 4 c; and FIGS. 4 g-4 i show SEM images of the junctions (FIG. 4g) and examples of both small area (FIG. 4 h) and large area (FIG. 4 i)SAM junctions;

FIG. 5 shows the distribution of junction resistance at room temperatureof SAM devices fabricated in accordance with the procedures of FIG. 4.The resistance range ΔR, corresponding to the lead resistance (shortedjunctions), extends between the vertical dashed lines. Horizontalrectangles 50 a-50 f show expected ranges of resistance assuming that(i) all self-aligned molecules inside junctions are bonded to bothelectrodes and (ii) tunneling conductance of 10⁻⁶-10⁻⁸Ω⁻¹ for T3molecules and 10⁻⁸-10⁻⁹Ω⁻¹ for C10 molecules. The inset between FIGS. 5a and 5 b shows results for junctions fabricated on an as-deposited Auelectrode;

FIG. 6 shows the distribution of junction resistance of SAM devices alsofabricated in accordance with the procedures of FIG. 4, but withclusters created at the interface between the top electrode and the SAMlayer. The top metal contact was formed by depositing a thin (0.5 nm) Aulayer first, letting the layer relax for time τ_(rel), and thendepositing a thicker (8 nm) thick Au layer. In FIG. 6 a τ _(rel)=1 hr,and a T3 SAM layer was deposited; in FIG. 6 b τ _(rel)=1 hr, and a C10SAM layer was deposited; in FIG. 6 c τ _(rel)=3 min, and T3 SAM layerwas deposited; in FIG. 6 d τ _(rel)=3 min, and a C10 SAM layer wasdeposited; FIG. 6 e shows the distribution of junction resistance fromthe devices of FIG. 6 c after soft electrical breakdown. The resistancerange ΔR, corresponding to the leads resistance (shorted junctions),extends between the vertical dashed lines. Horizontal rectangles 60 a-60e show expected ranges of resistance assuming that (i) only one moleculeper cluster forms good bonds at both ends and (ii) tunneling conductanceof 10⁻⁶-10⁻⁸Ω⁻¹ for T3 molecules and 10⁻⁸-10⁻⁹Ω⁻¹ for C10 molecules.FIG. 6 f is an STM image of clusters formed at the interface between theT3 SAM layer and the top Au layer.

FIG. 7 shows examples of characteristic transport behavior in thedevices fabricated according to the procedures of FIG. 4. In FIG. 7 acurves 71 and 72 show I-V characteristics measured on SAM FETs that bothincluded SAM layers of C10 molecules, but in one case the top electrodewas made of Ti (i.e., a C10-Ti junction; curve 71) and in the other itwas made of Ag (i.e., a C10-Ag junction; curve 72). Note, the currentscales for the two curves are different. Measurements were made at T=8K. The insets 71 i, 72 i show differential conductance dI/dV of curves71, 72, respectively, as a function of the source-to-drain voltage(V_(sd)); FIG. 7 b shows a family of I-V curves measured at differenttemperatures ranging from 6.5 K to 285 K on a SAM FET that included aC10-SAM layer and a Au top electrode (i.e., a C10-Au junction; and FIG.7 c shows a family of dI/dV curves measured at T=8 K on T3-Au junctionsat different gate voltages V_(g) ranging from +1.5 V to −1.5 V. Note thebreaks 73 and 75 in the left and right current axes, respectively, andfurther note the different scales of these axes (i.e., μA on the left;nA on the right); and

FIG. 8 schematically depicts metal assembly and penetration into the SAMlayer illustrating material modifications and interface topography thatwe studied. FIG. 8 a depicts metal filaments from the top electrodepenetrating through a SAM layer and shorting the device; FIG. 8 billustrates the smoothing effect of annealing the bottom electrode, andFIG. 8 c illustrates the formation of metal clusters at the interfacebetween the SAM layer and the top electrode.

DETAILED DESCRIPTION OF THE INVENTION General SAM Device Processing

With reference now to FIG. 1, there is shown a well-known, typicalsequence of process steps for forming a SAM layer on a metal layer. Theprocess begins with providing a body 10, which comprises a metal layer11 disposed on a top major surface of a substrate 12. Illustratively themetal layer 11 (e.g., Au, Ag, Ti, or Pt) is evaporated onto asemiconductor substrate (e.g., Si). The body 10 is then submerged into asolution containing organic molecules 14 that are capable ofself-assembly [e.g., a conjugated molecule such as terthiophenedithiol(T3), or a fully saturated molecule such as decanedithiol (C10)].Although both of these molecules are thiols, other organic molecules,such as primary, secondary and tertiary amines, isocyanides and carboxyacids are also suitable. For simplicity, however, the followingdescription assumes that the organic molecules are thiols.

As shown in FIG. 1 a, the thiol molecules 14 are randomly oriented atthe start, but when the substrate 10 is place into the solution, asshown in FIG. 1 b, some of the molecules 15 begin to adsorb onto themetal layer 11. After a suitable period of time (e.g., 5 min -24 hr), asshown in FIG. 1 c, the adsorbed thiol molecules 15 organize themselvesso that they are all oriented in essentially the same direction. (Thefree, non-adsorbed thiol molecules 14 remain randomly oriented in thesolution 13.) As a result, a nanoscale SAM layer 16 is formed on themetal layer 11, as shown in FIG. 1 d. The term nanoscale means thattypically SAM layers are on the order of only a few nanometers thick.The upper surface of the SAM layer 16 is referred to as a free surface16.1, whereas the lower surface of the SAM layer 16 is herein referredto as a bound surface 16.2, which is adsorbed onto the upper, majorsurface of metal layer 11.

To utilize the SAM intermediate structure of FIG. 1 d as a device, asshown in FIG. 2, typically a second metal layer 17 is formed (e.g., byevaporation) on the free surface 16.1 of SAM layer 16. From a deviceperspective, metal layers 11 and 20 function as electrodes, and asuitable voltage applied across the electrodes alters the conductance ofthe SAM layer 16. The device may serve as a diode 20, as shown in FIG.2, or as a FET 30, as shown in FIG. 3. In the latter case, FET 30includes, for example, a Si substrate 32, a silicon oxide insulatinglayer 38 formed on the top, major surface of substrate 32, and a firstpatterned metal electrode 33, 33.1 formed on oxide layer 38. Electrode33, 33.1 has an opening 34, and SAM layers 39, 39.1, are formed on thetop, major surfaces of electrodes 33, 33.1, respectively, but not in theopening 34. Note, the fact that there is no SAM layer in the opening 34is not essential for the proposed device operation. Finally, a secondmetal electrode 37, 37.1 is formed on a portion of the free surfaces ofSAM layers 39, 39.1, but the portion of interest is the small-areajunction J1 located between the right end of first electrode 33.1 andthe left end of second electrode 37. The small area junction J1 isrealized by means of a shadow mask 35 and oblique deposition of metal M2to form the second electrode 37, 37.1, which will be further explainedin conjunction with FIG. 4.

Using standard FET terminology, an FET with its junction defined by thedimension designated J1 includes a gate formed by the substrate 32, achannel formed by the SAM layer 36, a drain (or source) formed by thefirst metal electrode 33.1, and a source (or drain) formed by the secondmetal electrode 37. Of course, the area of the junction would be definedby the dimension J1 times a depth dimension (not shown) perpendicular tothe plane of the paper.

Although another junction J2 is also formed between first electrode 33and the right side of second electrode 37, it has a much larger area andis, therefore, of less interest from a device standpoint. The muchlarger area of junction J2 results in much higher lower resistance (mostlikely it is shorted). The device properties are defined by the muchhigher resistance of the smaller area junction J1.

Preferred Embodiment

Fabricating devices of type depicted in FIGS. 1-3 is conceptuallystraightforward, but practically difficult. As discussed above, one ofthe principal hurdles is to form electrodes on the extremely thin(nanoscale) SAM layer without shorting out the layer or dramaticallyincreasing the device conductance. To this end, I have found thatcertain aspects of the electrode formation process are important.

Thus, after forming the first metal electrode 33, 33.1 (FIG. 3) on oxidelayer 38, the electrode should be annealed. Suitable annealing increasesthe average crystal grain size of electrode 33, 33.1, and, in addition,reduces the roughness of its top major surface on which the SAM layer39, 39.1 forms (i.e., self-assembles). Illustratively, surface roughnesshaving an initial amplitude of 1-3 nm and periodicity of 20 nm isreduced to a post-anneal amplitude of 0.3 nm and increased to apost-anneal periodicity of 100's of nm. Suitable annealing conditionsinclude heating at a temperature of about 200-300 C for a time periodranging from a few minutes to less than 30 min; e.g., 250 C for 5 min;200 C for up to 30 min.

In addition, the second metal electrode 37, 37.1 should be deposited inat least two sequential depositions interrupted by a time intervalduring which essentially no deposition of metal takes place. During thisinterruption (or pause), metal clusters are formed on the portion of thebottom surface of electrode 37, 37.1. in contact with the free-surface16.1 of SAM layer 39, 39.1. In this regard, it is preferable that thesecond electrode 37, 37.1 comprises Au, but gold alloys may also besuitable. It is also preferred that the SAM material comprises a fullysaturated molecule (e.g., C10). Suitable interruption conditions includecompletely stopping deposition (e.g., evaporation) of second electrodemetal for at least 3 min but less than 60 min. Moreover, multipleinterruptions of second metal deposition may also be suitable.

Example

In order to determine the efficacy of my approach to fabricating metalelectrodes on nanoscale SAM devices, I studied the various phenomenaaffecting the conductance of SAM devices by systematically varying thegrowth conditions at the metal-molecule interface. Specifically, first Ioptimized the surface topography of the bottom metal electrode used forthe assembly of molecular layer by reducing the density of structuraldefects in the SAM layer. Reduced defect density dramatically reduceddiffusion of the top (second) metal contact 37 (FIG. 3) through the SAMlayer 36, increasing the device yield to >90%. Then, I altered thechemical bonding and surface topography at the interface between the topmetal and the SAM layer.

In the following experiments, various materials, dimension and operatingconditions are provided by way of illustration only and, unlessotherwise expressly stated, are not intended to limit the scope of theinvention.

Experimental Details

The general approach for SAM device fabrication was to perform the mostcritical patterning of nanometer features without having formed the SAMlayer yet. Then the SAM layer was self-assembled, and the devicestructure was completed with relatively non-invasive processing steps.Small shadow masks were defined within a stack 48 (FIG. 4) of insulatinglayers formed on Si substrates to obtain features below the lithographiclimit [5, 13-16]. In practice, a multiplicity of devices was formed on asingle substrate, but for simplicity the fabrication of only a singledevice is described below.

More specifically, a shown in FIGS. 4 a-4 c, a 200 nm thick layer 48.1of SiO₂ was grown on a degeneratively doped Si substrate 42 to isolatethe substrate from the devices (FETs). A small junction window (e.g., 5μm×5 μm; not shown) in SiO₂ layer 48.1 was defined by standardphotolithography and etching of layer 48.1. This window set the locationof the junctions to be formed later. Next, a 400 nm thick layer 48.2 ofSi₃N₄ was deposited on layer 48.1 (filling the junction window) and a150 nm thick layer 48.3 of SiO₂ was deposited on layer 48.2, therebydefining a stack 48 (FIG. 4 a) from which masks would ultimately beformed. Standard photolithography and etching were used to pattern thetop layer 48.3; that is, to form larger electrode windows 44.1 (e.g.,100 um×100 um) connected to elongated windows 44.2, which were separatedby a small shadow mask bridge 44.3. Next, as shown in FIG. 4 b, Si₃N₄layer 48.2 was selectively etched, thereby undercutting the top SiO₂layer 48.3 and exposing a portion of the top surface of Si substrate 42within the junction window. Finally, a high quality 10 nm thick SiO₂layer (not shown) was re-grown on the exposed Si substrate surfacewithin the junction window, thereby allowing use of the doped substrateas a gate electrode.

Fabrication of metal-SAM-metal junctions using this type of mask isillustrated in FIGS. 4 c-4 f, where FIG. 4 d zooms in on the centralregion of FIG. 4 c. First, bottom electrodes 43.1 and the elongatedsegments 43.2 were defined by vertical evaporation of metal M1 throughshadow mask 45 (FIG. 4 c). In the current study, the bottom electrodewas a polycrystalline bi-layer of Ti/Au (300 Å of Au on 5 Å of Ti),which will hereinafter be referred to simply as a Au electrode. Theelectrode segments 43.2 were separated by a bridge (or gap) 43.3 havinga width in the range of 100-300 nm. Next, SAM layers 49 (FIG. 4 e) weredeposited from solution in a conventional manner onto bottom electrodes43.1 (FIG. 4 c) and onto the electrode segments 43.2 (FIGS. 4 c and 4d). Two types of molecules, representing opposite ends of expectedelectronic functionality, were used in this study. Terthiophenedithiol(T3), synthesized using previously described methods [17], is aconjugated molecule with thiol groups responsible for chemicalattachment to metal electrodes. Decanedithiol (C10) is a fully saturatedmolecule with a length of 1.5 nm similar to the length of T3 molecules.

The substrates with bottom Au electrodes were soaked in atetrahydrofuran (THF) solution of the thiols (about 0.01 mM) at roomtemperature for 24 hours, then rinsed with THF, toluene and isopropanol.Both molecules formed SAM layers 49, 49.1 with thiol terminationsexposed at their top (free surface) interfaces as proven by nanotransferexperiments [18].

Finally, a top electrode 47, 47.1 was formed by evaporation of metal M2(FIG. 4 f) through the same shadow mask 45, but from an oblique angle.The size (area) of the junction is controlled by the size of the bridgeand the angle of the M2 metal evaporation.

SEM images of representative junctions are shown in FIGS. 4 g-4 i. FIG.4 g includes four junctions, the inset being a magnified view of one ofthem. FIG. 4 h shows a small area junction (e.g., ˜30×30 nm²), and FIG.4 h shows a larger area (˜300×300 nm²) junction.

A single chip contained 84 separate devices, allowing statisticalanalysis to be performed on nominally equivalent junctions and thejunction sizes to be varied. The electrical characterization did notrequire the removal of the mask stack or metal accumulated on topsurface of the mask, thus minimizing this potential source of damage orcontamination.

Experimental Results

In a first set of experiments, both T3 and C10 molecules were assembledon an as-deposited polycrystalline Au bottom electrode 43, 43.1 (FIG.4). The top electrode 47, 47.1 was an 8 nm thick layer of M2 metal (Auor Ag). Resistance of all junctions appeared to be indistinguishablefrom the lead resistance, which was in the range of 300Ω to 1 kΩ fordevices with different lead geometries. I concluded that the evaporatedM2 metal penetrated through the SAM layers 49, 49.1 shorting thedevices. These results are consistent with earlier observations of a lowyield of non-shorted multi-grain junctions formed with differentnano-templates [19]. The evaporated top M2 metal easily diffused neardefects in molecular packing induced by multiple grain boundaries of thebottom electrode 43, 43.1.

In the next set of experiments, the chips were annealed (250 C, 5 min)after deposition of the bottom polycrystalline Au electrode 43, 43.1.The annealing step modified the grain structure of the polycrystallineAu, making the grains smoother and the grain size larger. Thedistribution of device resistance measured at room temperature is shownin FIGS. 5 a-5 b. Although the variation was very broad, the yield ofnon-shorted devices was above ˜96% for T3 and above ˜92% for C10 SAMdevices. This result is much higher than in previous experiments byothers (0.5%-5%) with similar electrode arrangements [4, 5, 15].Surprisingly, the apparent median resistance for T3 SAM devices washigher than for C10 SAM devices, contrary to all expectations, whichclearly showed that the conductance of real junctions was not directlydetermined by the electronic structures of the molecules. No scaling ofthe resistance with the junction area was observed.

To study bond formation at the top interface M2 metals with differentchemical reactivities were overlaid on SAM layers. In particular, 7 nmthick overlayers of Au, Ag or Ti were deposited on separate SAM layers.The results are shown in FIG. 5. Silver is more reactive than Au, andtitanium is known to strongly react not only with thiol groups at thetop interface but also with carbon atoms [12]. FIGS. 5 c & 5 d show theelectrical properties of T3-Ag junctions, which were generally similarto those of T3-Au junctions (FIGS. 5 a & 5 b). But, FIG. 5 c shows thata significant percentage of the C10-Ag junctions were shorted. As shownin FIGS. 5 e & 5 f, the conductance of the junctions with Ti overlayerswas consistently higher. The overall histograms are very similar forboth T3 and C10 SAM devices; that is, compared to other cases shown inFIGS. 5 a-5 d, the histograms are narrow and are centered at closevalues of resistances.

The microscopic topography at the interface between the SAM layer 49,49.1 and the top electrode 47, 47.1 is generally unknown. In an attemptto control the topography, M2 metal clusters (e.g., FIG. 6 f) wereintentionally created at that interface. First, a thin (0.3-0.5 nm)overlayer of Au was evaporated on the free surface of SAM layer 49,49.1, simultaneously on the FET chips and on reference SAM layersassembled on an atomically flat Au substrate. The evaporation chamberwas vented, and the reference sample was used to examine the topographyof the Au overlayer by STM. Au clusters with an average diameter of ˜6nm were clearly seen (FIG. 6 f). After a 1 hr interruption (pause) thejunction fabrication was completed by evaporating a thicker (8 nm),second overlayer of Au on the first Au overlayer.

The electrical properties of these junctions (FIGS. 6 a & 6 b) weredramatically different from junctions formed with the uninterrupted Auevaporation (FIGS. 5 a & 5 b). All T3-SAM junctions were shorted (FIG. 6a), whereas all C10-SAM junctions were highly resistive (FIG. 6 b; forconvenience, all devices with R>10¹²Ω were lumped into a single bin).

In the next set of experiments, after deposition of a thin (0.5 nm)overlayer of Au, the evaporation was interrupted for only 3 min followedby continuous evaporation of a thicker (8 nm) layer of Au on top of thethin layer of Au. (The histograms are shown in FIGS. 6 c & 6 d). Theresults clearly fall between those fabricated using the continuous Auevaporation technique (FIG. 5) and those fabricated using theinterrupted (for 1 hr) Au evaporation technique (FIGS. 6 a & 6 b). Halfof the T3-Au junctions are not shorted (FIG. 6 c); and the C10-Aujunctions were less resistive on average (FIG. 6 d). The shorted T3-Aujunctions can be electrically driven into a more resistive state, asillustrated by the vertical arrow between FIG. 6 c and FIG. 6 e. Voltagepulses with ˜30-50 mV amplitude and rise time below 1 μs usuallytriggered modification of the shorted junctions. Applying dc voltage upto 1V did not change the junction conductance. The distribution ofresistances of junctions after the breakdown is shown in FIG. 6 e.

Junction resistance measured at room temperature only partlycharacterizes the transport properties. The conductance of the junctionsas a function of source-drain voltage and temperature was also studied.The specific details of current-voltage (I-V) curves variedsignificantly as can be expected from the broad distribution ofconductance values. Some representative results are illustrated in FIG.7.

Transport characteristics of all T3-Ti and C10-Ti junctions were quitesimilar, as were their I-V characteristics shown in FIG. 7 a. The topcurve 71 is typical of a C10-Ti junction, and the bottom curve 72 istypical of a C10-Ag junction. The functional dependence of this curvesis rather similar, but the absolute scales of their conductance differsby a factor of ˜1000. Conductance fell only by 5-15% as temperaturechanged from 300 K to 4.2 K. Low-temperature dI/dV curves were rathersmooth, with a small dip near V_(sd)=0 (insets, FIG. 7 a). The lowerconductance, the zero-bias dip, and the smooth dI/dV variation clearlydifferentiate these junctions from shorted ones. Weak temperaturedependence and zero-bias anomaly are the usual signatures of tunnelingconductance. Most of the non-shorted C10-Ag and all C10-Au_(clust)junctions also displayed insignificant temperature dependence, but thetunneling conductance in this case was lower by orders of magnitude incomparison with Ti overlayer junctions. A small percentage of othertypes of junctions also displayed weak temperature dependence ofconductance. Note, the subscript “clust” denotes Au with clusters formedat the interface between the SAM layer and the top electrode.

The transport properties of a majority of other junctions with Au and Agoverlayers were more complicated. I-V curves were usually linear at roomtemperature. Conductance measured at zero source-drain bias fellnoticeably with decreasing temperature (FIG. 7 b). Low-temperature I-Vcurves displayed a non-linear region with characteristic voltage scaleV_(sd)˜25-200 mV. This general behavior was typical for T3-Au, C10-Au,T3-Ag, T3-Au_(clust) junctions. Similar behavior has been observed inprevious studies of multi-grain junctions fabricated on the sharp quartztemplates [19] and has been analyzed in previous publications [19, 20].

Two separate conductance mechanisms contribute to the overall electricaltransport. The temperature dependent part of the conductance can beidentified as hopping transport, characterized by a small energy scalein the range ˜10-150 meV. The residual conductance observed at lowtemperature is a combination of direct tunneling between contacts,sequential tunneling through low-energy defect states and hopping. Therelative contributions of hopping and tunneling to the overallconductance varied broadly from sample to sample.

Finer differences between transport behavior in T3 and C10 SAM deviceswere seen in the low-temperature dI/dV curves (i.e., FIG. 7 c).Conductance peaks shown in FIG. 7 c were observed in most of the T3-Au,T3-Ag and T3-Au_(clust) junctions. The positions of the peaks on thedI/dV(V_(sd)) curves could be shifted by gate voltage in the case ofT3-Au and T3-Ag junctions. Such behavior is reminiscent ofsingle-electron charging of isolated islands. In T3-Au_(clust)junctions, the peaks were stronger relative to the smoother background,whereas the peak positions were usually insensitive to the gate voltage.No similar conductance peaks were observed in the majority of C10-Ausamples.

DISCUSSION

First, a comment on overall conductance values through the SAM layerscompared with previously published results. Commonly accepted [21]tunneling conductance per conjugated molecule of comparable length [22,23] is 10⁻⁶-10⁻⁸Ω⁻¹, and conductance per alkane molecule [24] is10⁻⁸-10⁻⁹Ω⁻¹. A medium size junction measuring ˜100 nm×100 nm contains˜5×10⁴ molecules. If one assumes that every molecule is well-bonded onboth sides, the median resistance of junctions is 20Ω-2Ω and 2-20 kΩfor, respectively, T3 and C10 junctions, as illustrated in FIG. 5 byhorizontal rectangles 50 a-50 f. In most cases, the median experimentalresistances were much larger than the estimations based on theliterature data. Certainly, the common assumption that all molecules areconnected to both contacts may be unrealistic, but the experiment withcluster formation in the Au layer at the top interface with the SAMlayer allowed me to reliably estimate the minimal number of connectedmolecules to be reliably estimated. Conservatively, I assumed that therewas just a single bond per metal cluster of the top contact, which meansthat a representative junction contains ˜300 well-bonded molecules. Thecorresponding resistance estimates were 3 kΩ-300 kΩ for T3 junctions,and 300 kΩ-3 MΩ for C10 junctions (shown in FIG. 6). Clearly, theresults show that the tunneling conductance of molecules is lower by 4-6orders of magnitude for both conjugated and saturated molecules, instrong contrast to the majority of previous calculations and experiments[21].

In fact, in the vast majority of devices the conductance associated withtunneling through the molecular orbitals could not be singled out. Highvalues of tunneling conductance measured in the junctions with Tioverlayers were unlikely related to the electronic structures of theoriginal molecules since no difference between conjugated and saturatedmolecules was seen in the experiments. Evaporated Ti reacted stronglywith organics [12] attacking the SAM and forming Ti carbides andoxycarbides. Tunneling conductance measured in all other junctions waslikely to be determined by the microscopic configuration of metalelectrodes that had partly penetrated the SAM, and/or a small number ofdefect states rather than by molecular states.

The essential material transformations defining the electronicproperties of molecular junctions are schematically illustrated in FIG.8. Structural defects in SAM layers 85 assembled on as-deposited Auelectrodes 82 allowed for easy diffusion (e.g., filaments 81.1) of thetop metal electrode 81 through the SAM layer. The SAM structure wassignificantly improved by annealing the bottom Au electrode 82 beforethe deposition of self-aligned molecules, as depicted by the smootherbottom Au electrode 84.1 of FIG. 8 b. The high yield of non-shorteddevices achieved by evaporation of Au on top of SAM layers suggests thatpractically all incident Au atoms were stopped at the top interface. Theoverall electrical properties of junctions formed with T3 and C10 SAMdevices were rather similar. I believe that during its growth andcrystallization, the Au overlayer penetrated deep into the SAM layer(FIG. 8 a), exerting substantial pressure and deforming the molecules.The microscopic details of the electrode topography were almostindependent of the molecule type in this particular case. Diffusion andgrowth of Ag overlayers differed depending on the SAM type. Agpenetrated alkane SAM layers more easily. Finally, evaporated Tistrongly reacted with the SAM layers, modifying electronic structurewith little discrimination between conjugated and saturated molecules.

Relaxation of the thin Au overlayer accumulated at the top molecularinterface and cluster formation resulted in two new phenomena. First,comparing properties of the junctions formed on C10 SAM layers, Isuggest that this relaxation significantly reduced stress at theinterface and the penetration of the top metal contact into the SAMvolume. The C10 junctions with a relaxed top interface were so resistivethat their conductance could not be reliably differentiated from apossible leakage through the substrate. Very different behavior was seenon conjugated SAM layers. Effectively, the clusters diffused through theSAM easier than separate Au atoms impinging the SAM layer during theevaporation. The cluster diffusion had to proceed along with aredistribution of molecules in the SAM layer. Apparently, theconfiguration with the clusters partly or fully submerged into theconjugated SAM layer lowered the total energy of the system. Theclusters that formed at the edge of a continuous Au top electrode andpartly penetrated into the SAM can account for the systematicobservation of conductance resonances sensitive to the gate voltage inT3 junctions.

Residual impurities, clusters, other low-energy defects and interfacetopography leading to different conductance mechanisms and broaddistribution of junction resistances enormously complicate a reliabledetermination of tunneling conductance through the molecular levels.While a significant disagreement with the literature data can be easilydemonstrated based on the full dataset, to estimate the molecularconductance I selected the more resistive junctions with I-V curvesdisplaying negligible contribution from the low-energy transportchannels. The estimates gave R_(T3)>10¹¹Ω and R_(C10)>10¹⁴-10¹⁵Ω for T3and C10, respectively. Simple approximation of tunneling under arectangular barrier is often useful to relate the values of tunnelingresistances with the energy structure. In such a model, R=R₀exp(βl),where R₀ is of the order of the quantum resistance, l is the length ofthe barrier, β=2(2m*E)^(1/2)/h is the tunneling decay parameter, E isthe barrier height and m* is the effective mass. Based on the estimatesof resistances, β_(C10)˜1.5 and β_(T3)˜1.1, and, assuming E_(C10)˜5 eVand E_(T3)=1.4 eV (˜½ of bandgap), m*_(C10)˜0.4m₀ and m*_(T3)˜0.8m₀,where m₀ is the free electron mass. Note that in other well-studiedtunnel barriers, such as AlO_(x) and SiO₂, the effective mass is usuallyclose to 0.5m₀ [25, 26]. Calculations of molecular tunneling if reducedto the simple single barrier approximation, typically predict muchsmaller m* values such as m* ˜0.2m₀ for alkanes and m*˜(0.06-0.25)m₀ fordifferent conjugated molecules [21, 24, 27].

The results clearly expose a variety of material transformations andself-organization processes occurring during integration of organic andinorganic components in nanoscale devices. These experiments are thefirst that systematically correlate the electrical properties of SAMdevices with the microscopic details of the metal-molecule interface. Ihave demonstrated that the generation of defects can be dramaticallyreduced for certain combinations of metals and molecules by changingsurface topography and growth conditions at the interface.

1. Apparatus comprising a substrate having a top surface and first metalelectrode disposed on at least a portion of said top surface, aself-assembled molecular layer disposed on a major surface of said firstmetal electrode, said molecular layer having a free surface, and asecond metal electrode having at least a portion thereof disposed onsaid free surface of said molecular layer, said portion of second metalelectrode including metal clusters.
 2. The apparatus of claim 1, whereinsaid first metal electrode has an annealed crystal structure.
 3. Theapparatus of claim 2, wherein said first electrode has a larger averagegrain size than non-annealed metal layers of the same composition andsame dimension.
 4. The apparatus of claim 1, wherein said firstelectrode, molecular layer and second electrode form a stack along adirection substantially perpendicular to said portion of said topsurface.
 5. The apparatus of claim 1, wherein said apparatus comprises adiode or a transistor having a channel, said molecular layer formingsaid channel.
 6. The apparatus of claim 5, wherein said second metalelectrode comprises Au and said molecular layer comprises a fullysaturated molecule.